Kerala Engineering and Medical Entrance Examination (KEAM) 2009 Questions on Digital Circuits

The following question appeared in Kerala Engineering Entrance 2009 Examination question paper:

The truth table for the following logic circuit is

The top AND gate gets inputs (NOT A) and B. The bottom AND gate gets inputs A and (NOT B). The outputs of the two AND gates are respectively [(NOT A) AND B] and [A AND (NOT B)]. These are the inputs for the final OR gate. The output of the final OR gate is [(NOT A) AND B] OR [A AND (NOT B)]. This is the Boolean expression for the XOR gate (exclusive OR gate, also termed EXOR gate). The truth table for the XOR gate is given in option (A).

Even if you don’t know the XOR gate and its truth table, you can substitute values 0 and 1 for the inputs A and B and find the output in each trial. You can easily arrive at the answer given in option (A).

The following question appeared in Kerala Medical Entrance 2009 Examination question paper:

If the two inputs of a NAND gate are shorted, the gate is equivalent to

(a) XOR

(b) OR

(c) NOR

(d) NOT

(e) AND

If both inputs of a two input NAND gate are shorted, both inputs get the same signal. Because of the NOT operation at the output side of the NAND, the output is the complement of the input. The circuit therefore behaves as a NOT gate [Option (d)].

Karnataka CET Questions (MCQ) on Digital Circuits

I give below 4 questions which appeared in Karnataka Common Entrance Test (CET) question papers of the years 2009, 2008, 2007 and 2006 respectively:

(1) In the following combination of logic gates, the outputs A, B and C are respectively

(1) 0, 1, 0

(2) 1, 1, 0

(3) 1, 0, 1

(4) 0, 1, 1

In circuit (A), the output of the input NAND gate is 0 since both inputs are 1. After inversion it becomes 1 and the final OR gate produces output 1.

In circuit (B), the output NAND gate gets 1 and 0 as its inputs and hence the final output is 1.

In the circuit (C), the NOR gate at the input side supplies 0 as one input to the AND gate at the output side. Hence the final output is 0.

Therefore, the correct option is (2).

(2) To get an output Y = 1 from the circuit shown, the inputs A, B and C must be respectively

(1) 0, 1, 0

(2) 1, 0, 0

(3) 1, 0, 1

(4) 1, 1, 0

In all cases the OR gate will provide a high (level 1) input to the AND gate at the output side. The AND gate should have both inputs at level 1 in order to have its output at 1. This is possible only if input C is 1. So the correct option is (3).

(3) The truth table given below is for

(A and B are the inputs, y is the output)

(1) NAND

(2) XOR

(3) AND

(4) NOR

The output y is the complement of AND operation and hence the answer is NAND [Option (1)].

(4) Identify the logic operation performrd by the cicuit given below

(1) NOT

(2) AND

(3) OR

(4) NAND

If you know De Morgan’s theorem, you will immediately obtain the answer as AND. The NOR gate at the output side gets inputs which are complement of A and complement of B. According to De Morgan’s theorem, (NOT A OR NOT B) is the same as [NOT (A AND B)]. Since the output gate is not an OR gate, but a NOR gate, the output is (A AND B).

Therefore, given circuit performs AND operation [Option (2)].

[If you do not know De Morgan’s theorem, you may try substituting values 0 and 1 for A and B to obtain the answer].